1. Field of the Invention
The present invention relates to a state indicating information setting circuit and a status bit setting circuit, and, in particular, to a state indicating information setting circuit and a status bit setting circuit responsive to a detection of a predetermined state by a predetermined state detecting part for setting predetermined state indicating information and then appropriately resetting the detection state in the state detecting part.
2. Description of the Related Art
A so-called read register circuit is a register from which a CPU can read out predetermined information provided in a peripheral circuit of a so-called UART (universal asynchronous receiver-transmitter). A specific example thereof is a circuit which provides a DCTS (delta clear to send) bit for an MSR (modem status register) providing an I/O port of a well-known 16450/16550 type UART.
Such a read register circuit is responsive to a detection of a status in a predetermined status detection part, which status occurs in a relating circuit as a predetermined monitoring object, for taking this state, turning on a so-called DCTS bit as state indicting information and thus enabling reading out of the bit from the external CPU.
With regard to the read register circuit, if the DCTS bit were read out by the CPU again after being once read out by the same CPU, a recognition error would occur, which may result in a damage exerted in the system around the CPU. In order to avoid such a situation, it is necessary to appropriately clear the once occurring state in the above-mentioned status detecting part from which the DCTS bit originates, so as to prevent the same status information from being taken in by the read register circuit again after once the DCTS bit is turned on.
However, if the timing of the clearing of the state in the status detecting part were too early, i.e., if the clearing operation on the status detecting part occurred before the status is properly taken in by the read register circuit once, it would prevent the status from being properly taken in by the read register circuit. In such a case, the DCTS bit might not be turned on at worst as a result. Especially, high speed operation of a computer has been demanded recently, and as a result, the above-mentioned problem tends to be more serious.
The requirements which should be satisfied by the DCTS bit of the above-mentioned MSR, which is one example of the above-mentioned DCTS bit, are as follows:
1) the status, i.e., a change in a CTS (clear to send) line in this case is detected, and the bit is turned on to “1”;
2) the bit is then turned off to “0” after the status is taken in with a predetermined register reading out signal, i.e., an MSR reading out signal in this example; and
3) even if the bit=1 cannot be read out by the register reading out signal in case the status signal changes during the reading out of the status with the register reading out signal, the bit=1 can be read out with the subsequent register reading out signal.
Japanese laid-open patent application No. H10-41804 for example discloses a method of clearing the status detection state for a read registrar circuit mentioned above. A configuration applying the method thus disclosed for clearing the status detection state after the status is read by the register reading signal as for an interface bit provided in an LSR (line status register), the above-mentioned MSR (modem status register) or so, for example, will now be discussed. In this case, same as the above, it is assumed that the bit satisfies the following requirements:
1) the bit is turned on to “1” (in other words, ‘the bit is set’) in response to a change in the input signal CTS (L→H, or H→L);
2) upon provision of the MSR reading out signal, the bit can be read out externally, i.e., by a CPU or the like;
3) upon provision of the MSR reading out signal, after the bit is read out externally once, the bit is turned off to “0” (i.e., ‘the bit is cleared or cancelled’) after the reading out; and
4) during provision of the MSR reading out signal, in case the input signal CTS changes, even when the bit=1 cannot be read out in the current reading out operation, the bit=1 can be read out in the subsequent reading out operation.
FIG. 1 shows a DCTS bit setting circuit configured applying the concept disclosed by the above-mentioned Japanese laid-open patent application No. H10-41804. FIG. 2 shows operation time chart in the circuit shown in FIG. 1. In the figures, ‘ff1’ and ‘ff2’ denote D-FFs (D-flip-flops), respectively. The operation of this circuit will now be described.
In FIG. 2, in Steps (1) through (9), DCTS bit=1 is read out with the MSR reading out signal after the input signal CTS changes, and DCTS bit=0 is read out with the subsequent MSR reading out signal. Further, in Steps (10) through (17), when the input signal CTS changes during provision of the MSR reading out signal, DCTS bit=0 is read out with this MSR reading out signal, and then, with the subsequent MSR reading out signal, DCTS bit=1 is read out. These operations will now be described specifically step by step.
In Step (1), the input signal CTS changes, and in Step (2), a one shot pulse generating circuit 10 detects this change in the CTS signal, and generates a one shot pulse. In Step (3), the one shot pulse resulting from the detection of the CTS change is input to an S input terminal of a flip-flop ff1, and as a result, ff1=H occurs. In Step (4), MSR reading out signal=L occurs, and in Step (5), a flip-flop ff2 responds thereto and takes in the value of ff1=H. As a result, during MSR reading out signal=L, a bus driver BS opens so that DCTS bit=1 (=ff2) is read out by a CPU (see FIG. 2, (f)).
In Step (6), ff1=L occurs due to a change of the MSR reading out signal into the L level. In Step (7), MSR reading out signal=H occurs, and then, in Step (8), when MSR reading out signal=L occurs, ff2 takes in the value of ff1=L due to the change of the MSR reading out signal into the L level in Step (9). As a result, the bus driver BS opens during MSR reading out signal=L, and DCTS bit=0 (=ff2) is read out (see FIG. 2, (f)). In Step (10), when MSR reading out signal=L occurs, in response thereto, in Step (11), ff2 takes in the value of ff1=L. As a result, also in this case, during MSR reading out signal=L, DCTS bit=0 (=ff2) is read out (see FIG. 2, (f)).
Then, when the input signal CTS changes in Step (12), the one shot pulse generating circuit 10 detects it in Step (13), and generates a one shot pulse. In Step (14), this is input to the S input terminal of ff1, and thus, ff1=H results. Then, in Step (15), MSR reading out signal=H occurs, and in Step (16), MSR reading out signal=L occurs. In response thereto, in Step (17), ff2 takes in the value of ff1=H. As a result, during MSR reading out signal=L, DCTS bit=1 (=ff2) is read out. Further, in Step (18), due to the change of the MSR reading out signal into the L level, ff1=L results.
FIG. 3 shows a circuit configuration of another example of a DCTS bit setting circuit for an MSR applying a concept disclosed by Japanese laid-open patent application No. H2-44428. FIG. 4 shows an operation time chart in this circuit. In these figures, ‘ff1’ and ‘ff2’ denote respective SR latch circuit devices, and ‘ff3’ denotes a D latch circuit device. Operations in the circuit are as follows:
In Steps (1) through (15) in FIG. 4, DCTS bit=1 is read out with an MSR reading out signal after a CTS line level acting as an input signal changes, and then, with the subsequent MSR reading out signal, DCTS bit=0 is read out. In Step (16) through (26), when the input signal CTS level changes during provision of the MSR reading out signal, DCTS bit=0 is read out at the time of provision of the MSR reading out signal, and then, upon the subsequent provision of the MSR reading out signal, DCTS bit=1 is read out. The respective steps will now be described step by step.
In Step (1), when the input signal CTS changes, a one shot pulse generating circuit 10 detects the change in the input signal CTS in Step (2), and outputs a CTS change detection result=H pulse. In Step (3), this signal is input to an S terminal of ff2, and ff2=H results. In Step (4), signal=L obtained from inverting the MSR reading out signal by a NOT circuit device 20 is input to a G terminal of ff3, so that ff3 opens, and thus, ff2=ff3=H results.
In Step (5), MSR reading out signal=L occurs, and as a result, the signal=H resulting from inversion of the MSR reading out signal by the NOT device 20 is input to the G terminal of ff3 so that ff3 opens in Step (6), and as a result, ff3 holds ff2=H. As a result, during the bus driver BD being opened due to the MSR reading out signal=L at this time, DCTS bit=1, i.e., the output of ff3 is read out (see FIG. 4, (h)).
In Step (7), MSR reading out signal=H is input to an S terminal of ff1, a signal=L resulting from inversion of the ff3 is input to an R terminal of ff1, and thus, ff1=H results. After that, in Step (8), MSR reading out signal=H occurs, and in Step (9), the signal=L resulting from inversion of this MSR reading out signal and the signal=L resulting from inversion of ff1 are input to an OR circuit device 30. As a result, DCTS bit clear signal=H occurs which is the output of the OR device 30.
In Step (10), the above-mentioned DCTS bit clear signal is input to the R terminal of ff2, and thus, ff2=L results. In Step (11), signal=L resulting from inversion of the MSR reading out signal is input to the G terminal of ff3, so that ff3 opens. As a result, ff3=ff2=L results. In Step (12), signal=H resulting from inversion of this ff3 is input to the R terminal of ff1, and thus, ff1=L results. Then, in Step (13), the signal L inverted from MSR reading out signal and the signal H inverted from ff1 are input to the OR device 30, and thus, DCTS bit clear signal=L results which is the output of the OR device 30.
Then, in Step (14), when MSR reading out signal=L occurs, signal=H inverted from this MSR reading out signal by the NOT device 20 is input to the G terminal of ff3 so that ff3 closes in Step (15), and thus ff3 holds ff2=L. As a result, during the BD being opened by the MSR reading out signal=L at this time, DCTS bit=0 (=ff3) is read out (see FIG. 4, (h)).
Then, in Step (16), when MSR reading out signal=L occurs, signal=H inverted from the MSR reading out signal is input to the G terminal of ff3, which causes the ff3 to close, and thus, the ff3 holds ff2=L in Step (17). As a result, the BD opens during MSR reading out signal=L at this time, and thus, DCTS bit=0 (=ff3) is read out (see FIG. 4, (h)).
Then, in Step (18), when the input signal CTS level changes, the one shot pulse generating circuit 10 detects this change in the input signal CTS in Step (19), and generates an H pulse as a CTS change detection result. In Step (20), the H pulse as the CTS change detection result is input to the S terminal of the ff2, which results in ff2=H. Then, in Step (21), MSR reading out signal=H occurs, and in Step (22), the inverted signal=L therefrom by the NOT device 20 is input to the G terminal of the ff3, which causes the ff3 to open, and thus, the ff3 takes in the value of ff2=H.
Then, in Step (23), MSR reading out signal=L occurs, inverted signal=H thereof is input to the G terminal of the ff3, which causes the ff3 to open, and thus, the ff3 holds the above-mentioned ff2=H. As a result, during the BD being opened due to MSR reading out signal=L at this time, DCTS bit=1 (=ff3) is read out.
Then, in Step (25), inverted signal=H from the above-mentioned MSR reading out signal is input to the S terminal of the ff1 and also inverted signal=L from the ff3 is input to the R terminal of the ff1, which results in ff1=H. Then, in Step (26), when MSR reading out signal=H occurs, inverted signal=L therefrom and inverted signal=L from the ff1 result in DCTS bit clear signal=H which is the inverted output of the OR device 30, in Step (27).
In Step (28), this DCTS bit clear signal is input to the R terminal of the ff2, which causes ff2=L, and in Step (29), inverted signal=L from the MSR reading out signal is input to the G terminal of the ff3, which opens the ff3, and thus, the ff3 takes in the value of ff2=L. Then, in Step (30), inverted output signal=H of the ff3 is input to the R terminal of the ff1, and thus, ff1=L results. Then, in Step (31), inverted signal=L of the MSR reading out signal and inverted signal=L of the ff1 cause DCTS bit clear signal=L which is the inverted output of the OR device.
Thus, in both the example of FIGS. 1 and 2 and the example of FIG. 3 and 4, in response to the change in the CTS line level (rising edge), the DCTS bit “1” is read out with an immediately coming L level of the MSR reading out signal, and then, the DCTS bit is returned to “0” with an immediately coming L level of the MSR reading out signal. Similarly, in response to the change in the CTS line level (decaying edge), the DCTS bit “1” is read out with an immediately coming L level of the MSR reading out signal, and then, the DCTS bit is returned to “0” with an immediately coming L level of the MSR reading out signal. Accordingly, the above-mentioned requirements for a DCTS bit are satisfied.
Further, other than the above-mentioned two prior art documents, Japanese laid-open patent applications Nos. H10-240497 and H07-56756 also disclose the background arts.